Shiga, Japan

Katsumi Terada

This inventor holds 7 USPTO granted patents and 1 published patent application. Top assignee: Toray Engineering Company, Limited. Active years: 2005-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Katsumi Terada. Retrieved from https://idiyas.com/inventor/katsumi-terada-v2uthzis

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 7 

% Patents Active = 42.9

Average Co-Inventor Count = 2.2

ph-index = 3

Forward Citations = 19(Granted Patents)


Location History:

  • Shiga, JP (2005 - 2010)
  • Otsu, JP (2017 - 2019)

Company Filing History:


Years Active: 2005-2025

Loading Chart...
7 patents (USPTO):Explore Patents

Title: Innovations of Katsumi Terada

Introduction

Katsumi Terada is a notable inventor based in Shiga, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of seven patents. His work focuses on advanced mounting devices and methods that enhance the efficiency and precision of semiconductor assembly.

Latest Patents

One of his latest patents is a mounting device that comprises a substrate stage, a mounting head, an elevating unit, a recognition mechanism, and a control unit. The recognition mechanism acquires position information about a chip recognition mark and a substrate recognition mark using an imaging unit. The control unit calculates an amount of positional deviation between a chip component and a substrate from the position information about the chip recognition mark and the substrate recognition mark. It performs alignment by driving the mounting head and/or the substrate stage according to the amount of the positional deviation. The chip component and the substrate are brought closer to each other, and the alignment is performed in a state in which the imaging unit simultaneously images the chip recognition mark and the substrate recognition mark within a depth of field. After this, the chip component and the substrate are brought into close contact with each other.

Another significant patent involves a mounting device that includes a thermocompression bonding head, a pressure reduction mechanism, and a resin sheet feed mechanism. The thermocompression bonding head is configured to heat a semiconductor chip while holding it and to bond the semiconductor chip to a joined piece by compression. The thermocompression bonding head has a suction hole in a face that holds the semiconductor chip. The pressure reduction mechanism communicates with the suction hole and is configured to reduce pressure inside the suction hole. The resin sheet feed mechanism is designed to supply a resin sheet between the thermocompression bonding head and the semiconductor chip. An electrode that protrudes from the top face of the semiconductor chip is bonded by thermocompression after being embedded in the resin sheet.

Career Highlights

Katsumi Terada is currently employed at Toray Engineering Company, Limited, where he continues to innovate in the field of semiconductor technology. His work has been instrumental in developing advanced mounting techniques that improve the reliability and performance of semiconductor devices.

Collaborations

He has collaborated with notable colleagues such as Akira Yamauchi and Takashi Hare, contributing to various projects that push the boundaries of semiconductor technology.

Conclusion

Katsumi Ter

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…