This inventor holds 1 USPTO granted patent and 11 published patent applications. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.
Company Filing History:
Years Active: 2026
Title: Innovations by Inventor Kai-Min Chien
Introduction
Kai-Min Chien is an inventor based in New Taipei City, Taiwan. He is known for his contributions to the field of semiconductor devices. Although he currently holds no granted patents, his work in developing innovative methods for semiconductor structures is noteworthy.
Latest Patent Applications
Kai-Min Chien has filed several patent applications, including:
1. **SEMICONDUCTOR DEVICE STRUCTURE WITH NANOSTRUCTURE AND METHOD FOR FORMING THE SAME** - This application describes a method for forming a semiconductor device structure. The method involves providing a substrate, a first nanostructure, a second nanostructure, and a first gate stack. The first nanostructure is positioned between the substrate and the second nanostructure, with the first gate stack wrapped around both nanostructures. The process includes removing the first gate stack and end portions of the first nanostructure, partially removing the second nanostructure to create a rounded corner, and forming a second gate stack over the substrate that wraps around the second nanostructure.
2. **PROFILES OF GATE STRUCTURES IN SEMICONDUCTOR DEVICES** - This application discloses a semiconductor device and a method for its fabrication. The device includes a substrate, a semiconductor layer, a source/drain region, a gate structure, and an interfacial spacer layer with a triangular cross-sectional profile. The gate spacer consists of two portions, each with distinct bottom surface profiles, enhancing the overall functionality of the semiconductor device.
Conclusion
Kai-Min Chien's innovative approaches to semiconductor device structures highlight his potential impact on the field, despite not having any granted patents at this time. His latest patent applications reflect a commitment to advancing technology in semiconductor design and fabrication.