Singapore, Singapore

Jun Sheng Ng

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Tetramem Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jun Sheng Ng. Retrieved from https://idiyas.com/inventor/jun-sheng-ng

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Jun Sheng Ng: Advancing Error Correction for Memory Devices

Introduction

Jun Sheng Ng is an inventor based in Singapore. His patent work addresses error detection and correction in multi-level cell-based memory devices. He is associated with Tetramem Inc. and has 1 patent listed in the information provided.

Latest Patents

Ng’s patent, “Enhanced Error Correction Code for Error Detection and Correction in Multi-Level Cell-Based Memory Devices,” describes methods for improving the reliability of data stored in multi-level cell memory. The approach uses Reed-Solomon error correction code to calculate an error value and locate an error in data received by an ECC decoder.

The method classifies errors as no error, a single-symbol error, or multiple-symbol errors, using a +1/−1 error constraint. When multiple-symbol errors are identified, the system repeats the read from the memory device. This process is designed to support more effective error detection and correction.

Career Highlights

Ng’s listed patent focuses on memory reliability and hardware-based error correction. His work combines Reed-Solomon coding with error classification and a repeat-read response to address errors in multi-level cell-based storage.

Collaborations

Ng is associated with Tetramem Inc. The provided information also identifies Lei Liu and Yudi Dou as coworkers.

Conclusion

Jun Sheng Ng’s patent highlights an approach to improving error handling in multi-level cell-based memory through error classification, Reed-Solomon coding, and repeated reads when multiple-symbol errors occur.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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