Hillsboro, OR, United States of America

Joseph Brice

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Intel Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Joseph Brice. Retrieved from https://idiyas.com/inventor/joseph-brice

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Joseph Brice - Innovator in Integrated Circuit Structures

Introduction

Joseph Brice is an inventor based in Hillsboro, OR (US). He has made significant contributions to the field of integrated circuit structures. His innovative approach focuses on the fabrication of gate-all-around integrated circuit structures, which are essential for advancing semiconductor technology.

Latest Patent Applications

Joseph Brice's notable patent application is titled "FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING PRE-SPACER DEPOSITION CUT GATES." This application describes integrated circuit structures that include a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is positioned over the first vertical arrangement, while a second gate stack is over the second vertical arrangement. The design features a gap between the ends of the two gate stacks. Additionally, the structure incorporates a dielectric component that provides gate spacers along the sidewalls of both gate stacks, with a third portion filling the gap, ensuring continuity among the components.

Conclusion

Joseph Brice's work in integrated circuit structures showcases his innovative spirit and dedication to advancing technology. His contributions, particularly in the area of gate-all-around structures, highlight the importance of research and development in the semiconductor industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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