The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2026

Filed:

Aug. 23, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Megan Beck, Hillsboro, OR (US);

Joseph Brice, Hillsboro, OR (US);

Ryan Wood, Beaverton, OR (US);

Krishna T. Marla, Portland, OR (US);

Derek Caselli, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 30/43 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 30/43 (2025.01); H10D 30/6215 (2025.01); H10D 62/119 (2025.01);
Abstract

Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion providing a gate spacer along sidewalls of the first gate stack, a second portion providing a gate spacer along sidewalls of the second gate stack, and a third portion filling the gap, the third portion contiguous with the first and second portions.


Find Patent Forward Citations

Beck, Megan. (2026). Fabrication of gate-all-around integrated circuit structures having pre-spacer deposition cut gates with etch back process (U.S. Patent No. 12660245). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12660245

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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