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For the Inventor, By the Inventor

Davis, CA, United States of America

Jose P Allarey

This inventor holds 23 USPTO granted patents, primarily in Microprocessor Optimization. Top assignee: Intel Corporation. Active years: 2009-2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jose P Allarey. Retrieved from https://idiyas.com/inventor/jose-p-allarey

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 23

% Patents Active = 60.9

Average Co-Inventor Count = 2.8

ph-index = 8

Forward Citations = 156(Granted Patents)


Location History:

  • Rancho Cordova, CA (US) (2013)
  • Davis, CA (US) (2009 - 2018)

Company Filing History:

goldMedal23 out of 56,290 
 
Intel Corporation
 patents

Years Active: 2009-2018

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Areas of Expertise:
Turbo Performance
Low Power Mode
Dynamic Power Reduction
Microprocessor
Cache Preservation
Zero Voltage State
Multi-Core Performance
Frequency Optimization
23 patents (USPTO):Explore Patents
1. 9984038 - Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor (2018-05-29),
2. 9904346 - Methods and apparatus to improve turbo performance for events handling (2018-02-27),
3. 9280172 - Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor (2016-03-08),
4. 9274592 - Technique for preserving cached information during a low power mode (2016-03-01),
5. 9098274 - Methods and apparatuses to improve turbo performance for events handling (2015-08-04),
6. 9092218 - Methods and apparatus to improve turbo performance for events handling (2015-07-28),
7. 9081575 - Method and apparatus for a zero voltage processor sleep state (2015-07-14),
8. 8806248 - Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor (2014-08-12),
9. 8769323 - Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor (2014-07-01),
10. 8732399 - Technique for preserving cached information during a low power mode (2014-05-20),
11. 8707066 - Method and apparatus for a zero voltage processor sleep state (2014-04-22),
12. 8560871 - Method, apparatus, and system for optimizing frequency and performance in a multidie microprocessor (2013-10-15),
13. 8560869 - Dynamic power reduction (2013-10-15),
14. 8527709 - Technique for preserving cached information during a low power mode (2013-09-03),
15. 8516285 - Method, apparatus and system to dynamically choose an optimum power state (2013-08-20),

Title: Inventor Jose P Allarey

Introduction: Jose P Allarey is a renowned inventor based in Davis, California. He is known for his innovative contributions to various fields.

Latest Patents: Jose P Allarey holds several patents in the areas of technology and engineering, showcasing his dedication to pushing the boundaries of innovation.

Career Highlights: Throughout his career, Jose P Allarey has demonstrated a keen ability to transform ideas into tangible inventions that have made a significant impact in the industry.

Collaborations: Jose P Allarey has collaborated with leading research institutions and companies to further develop his inventions, highlighting his commitment to advancing technology through partnerships.

Conclusion: Inventor Jose P Allarey's passion for innovation and his impressive track record of patents solidify his position as a key figure in the world of inventors.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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