The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 14, 2015
Filed:
Apr. 16, 2014
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Jose Allarey, Davis, CA (US);
Sanjeev Jahagirdar, Folsom, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 11/14 (2006.01); G06F 12/08 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3287 (2013.01); G06F 1/3203 (2013.01); G06F 1/3243 (2013.01); G06F 1/3246 (2013.01); G06F 1/3275 (2013.01); G06F 1/3296 (2013.01); G06F 11/1441 (2013.01); G06F 12/084 (2013.01); G06F 12/0875 (2013.01); G11C 7/1072 (2013.01); G06F 2212/281 (2013.01); G06F 2212/305 (2013.01); Y02B 60/1239 (2013.01); Y02B 60/1285 (2013.01); Y02B 60/32 (2013.01);
Abstract
Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A voltage regulator may be coupled to a processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero while an external voltage is continuously applied to a portion of the processor to save state variables of the processor during the zero voltage management power state.