San Jose, CA, United States of America

Jong Oh Lee

This inventor holds 2 USPTO granted patents. Top assignees: Winbond Electronics Corporation, Windbond Electronics Corp.. Active years: 2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jong Oh Lee. Retrieved from https://idiyas.com/inventor/jong-oh-lee-hy8cxc2x

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 1.5

ph-index = 1

Forward Citations = 14(Granted Patents)


Company Filing History:


Years Active: 2016

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2 patents (USPTO):Explore Patents

Title: Jong Oh Lee: NAND Flash Memory Inventor

Introduction

Jong Oh Lee is an inventor associated with San Jose, California. His work includes patent inventions focused on NAND flash memory architecture and circuitry. Lee is credited with 2 patents.

Latest Patents

“Page Buffer Circuit for NAND Flash Memory” describes a page-buffer design for a NAND flash memory array. Its components—including switches, a latch, and data nodes—support reading and writing data between a selected memory cell and an input/output node.

“NAND Flash Memory Array Architecture Having Low Read Latency and Low Program Disturb” presents an architecture intended to reduce read latency while preventing inadvertent programming and program disturb. It combines small NAND strings, interleaved dual planes, partitioned arrays, selectively coupled local bit lines, and counter-biasing. The design aims to improve access speeds while retaining NAND flash’s density and power advantages.

Career Highlights

Lee’s listed company affiliations include Winbond Electronics Corporation. The supplied information also lists “Windbond Electronics Corp.,” which appears to be a variant spelling of the same company name.

Collaborations

Lee’s listed coworkers include Anil Gupta and Dae Hyun Kim.

Conclusion

Jong Oh Lee’s patent work addresses key NAND flash memory challenges by combining circuit-level techniques with array architectures designed to improve speed and reliability.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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