Company Filing History:

14 out of 164,197

International Business Machines Corporation

patents

2 out of 1,855

Adeia Semiconductor Bonding Technologies Inc.

patents

Years Active: 2016-2021

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16 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 11101357 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2021-08-24),

2. 10734492 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2020-08-04),

3. 10381452 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2019-08-13),

4. 10374048 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2019-08-06),

5. 10367072 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2019-07-30),

6. 9922831 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2018-03-20),

7. 9859122 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2018-01-02),

8. 9837319 - Asymmetric high-K dielectric for reducing gate induced drain leakage (2017-12-05),

9. 9768071 - Asymmetric high-K dielectric for reducing gate induced drain leakage (2017-09-19),

10. 9721843 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2017-08-01),

11. 9685379 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2017-06-20),

12. 9577061 - Asymmetric high-K dielectric for reducing gate induced drain leakage (2017-02-21),

13. 9570354 - Asymmetric high-K dielectric for reducing gate induced drain leakage (2017-02-14),

14. 9559010 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2017-01-31),

15. 9543213 - Asymmetric high-k dielectric for reducing gate induced drain leakage (2017-01-10),

Title: Innovations of Jonathan T Shaw

Introduction

Jonathan T Shaw is a notable inventor based in Rego Park, NY (US). He has made significant contributions to the field of semiconductor technology, holding a total of 16 patents. His work primarily focuses on enhancing the performance and efficiency of high-k MOSFETs.

Latest Patents

One of his latest patents is titled "Asymmetric high-k dielectric for reducing gate induced drain leakage." This invention discloses an asymmetric high-k dielectric designed to reduce gate induced drain leakage in high-k MOSFETs. The method involves performing an implant process on a high-k dielectric sidewall of a gate structure. Additionally, it includes an oxygen annealing process to grow an oxide region on the drain side of the gate structure while inhibiting oxide growth on the source side adjacent to the source region.

Career Highlights

Throughout his career, Jonathan has worked with prominent companies such as IBM and Adeia Semiconductor Bonding Technologies Inc. His experience in these organizations has allowed him to develop innovative solutions that address critical challenges in semiconductor manufacturing.

Collaborations

Jonathan has collaborated with several talented individuals in the industry, including Anthony I Chou and Arvind Kumar. These partnerships have contributed to the advancement of his research and the successful development of his patents.

Conclusion

Jonathan T Shaw's contributions to the field of semiconductor technology are noteworthy. His innovative patents and collaborations reflect his commitment to advancing technology and improving device performance.

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