John Valliant

Title: Innovations by John Valliant in Integrated Circuit Technology

Introduction

John Valliant is an accomplished inventor based in Santa Cruz, California. He has made significant contributions to the field of integrated circuit technology, particularly in the area of die thinning and polishing processes. With a total of two patents to his name, Valliant's work has had a notable impact on the efficiency and reliability of chip repair and failure analysis.

Latest Patents

Valliant's latest patents include a method and apparatus for global die thinning and polishing of flip-chip packaged integrated circuits. This innovative process is designed to provide a reliable and inexpensive solution for thinning integrated circuit dies to a target thickness of 10 microns while maintaining a yield of at least 80%. The method involves exposing the backside of the flip-chip packaged die and mounting it on a lapping machine. The thickness of the die is measured at multiple locations, and the lapping machine grinds the exposed surface to a thickness slightly greater than the target. After polishing, the thickness is measured again with high accuracy, and the process is repeated until the desired thickness is achieved.

Career Highlights

Throughout his career, John Valliant has worked with notable companies such as Nptest, Inc. and Credence Systems Corporation. His experience in these organizations has allowed him to refine his skills and contribute to advancements in integrated circuit technology.

Collaborations

Valliant has collaborated with various professionals in his field, including Chun-Cheng Tsao, enhancing the innovation process through teamwork and shared expertise.

Conclusion

John Valliant's contributions to the field of integrated circuits through his innovative patents and career experiences highlight his role as a significant inventor in this technology sector. His work continues to influence the efficiency of chip repair and failure analysis processes.