John Harold Downey

Title: John Harold Downey: Innovator in Circuit Design Verification

Introduction

John Harold Downey is a notable inventor based in San Jose, CA. He has made significant contributions to the field of circuit design verification, holding 2 patents that enhance the capabilities of hardware verification languages.

Latest Patents

One of his latest patents is titled "Method and apparatus for adaptive verification of circuit designs." This invention introduces new capabilities to a Hardware Verification Language (HVL) that facilitate the monitoring of a device under test (DUT). The HVL language supports Object-Oriented Programming (OOP), and within this framework, Downey's invention provides a monitoring facility that consists of three main stages: Coverage Definitions, Coverage Instantiation and Triggering, and Coverage Feedback. Each coverage definition acts similarly to an OOP class definition, declaring "monitor bins" associated with specific behaviors of state variables. The instantiation of a coverage definition produces a coverage instance, allowing for concurrent monitoring of the DUT's responses to stimuli.

Another significant patent is "Method and apparatus for event simulation." This invention outlines a method for inserting an event into a simulation time queue, represented by a tree structure. The structure includes a top node that represents the total number of time slices to be simulated, with intermediate nodes representing subsets of these time slices. The method involves determining the current location within the tree structure and adding events to the appropriate event locations based on the time slices.

Career Highlights

John Harold Downey is currently employed at Synopsys, Inc., where he applies his expertise in circuit design verification. His work has been instrumental in advancing the field and improving the efficiency of simulation processes.

Collaborations

Throughout his career, Downey has collaborated with notable colleagues, including Won Sub Kim and Daniel Marcos Chapiro. These collaborations have contributed to the development of innovative solutions in circuit design.

Conclusion

John Harold Downey's contributions to circuit design verification through his patents and work at Synopsys, Inc. highlight his role as a key innovator in the field. His inventions continue to influence the way hardware verification is approached, ensuring more efficient and effective design processes.