Method and apparatus for adaptive verification of circuit designs

Abstract

The present invention adds capabilities to a Hardware Verification Language (HVL) which facilitate the monitoring of a device under test (DUT). The HVL language supports Object-Oriented Programming (or OOP). Within this OOP framework, the present invention provides a monitoring facility comprised of three main stages: i) Coverage Definitions, ii) Coverage Instantiation and Triggering and iii) Coverage Feedback. A coverage definition is very similar to an OOP class definition, but does not contain methods or variables. Instead, the basic purpose of a coverage definition is to declare “monitor bins” in terms of a state variable. Essentially, each monitor bin declaration has a unique bin name which is associated with a particular behavior of the state variable and the unique bin name is used to record the state variable's behavior. Instantiation of a coverage definition produces a coverage instance. Two key instantiation parameters are: an actual state variable that is to be monitored by the instance and a trigger expression which determines when the state variable of the instance is to be monitored. Instantiating means that a concurrent, non-terminating, “coverage instance process” is also forked off. The “foreground” thread of control which forked off the coverage instance process may continue to operate and subject a DUT to stimuli. The DUT's responses to such stimuli may be monitored by the coverage instance process and stored as data associated with the coverage instance. The same foreground thread of control subjecting the DUT to stimuli can also query the resulting state of the coverage instance's data. This ability to query a coverage instance's data make possible “closed loop” testing since the foreground thread of control can subsequently alter further stimuli generated for the DUT based upon the results of its query.