Hillsboro, OR, United States of America

John Fretwell

This inventor holds 1 USPTO granted patent. Top assignee: Fei Comapny. Active years: 2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: John Fretwell. Retrieved from https://idiyas.com/inventor/john-fretwell-utty60sw

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1


Company Filing History:


Years Active: 2022

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1 patent (USPTO):Explore Patents

Title: John Fretwell: Innovator in Wafer Defect Inspection

Introduction

John Fretwell is an accomplished inventor based in Hillsboro, OR (US). He has made significant contributions to the field of semiconductor manufacturing, particularly in the area of wafer defect inspection. His innovative methods have the potential to enhance the quality control processes in the industry.

Latest Patents

John Fretwell holds a patent for a "Method and system for wafer defect inspection." This patent describes methods for locating and characterizing defects in substrates. The process involves performing a first scan to create a defect map, followed by a second scan of specific regions to produce electron channeling contrast (ECC) images. These images are crucial for characterizing defects, which can be further analyzed using additional techniques.

Career Highlights

Throughout his career, John has focused on improving inspection methods in semiconductor manufacturing. His work has led to advancements that help in identifying defects more accurately and efficiently. With a patent count of 1 patent, he has established himself as a notable figure in his field.

Collaborations

John has collaborated with talented individuals such as Roger Louis Alvis and Laurens Kwakman. These partnerships have contributed to the development of innovative solutions in wafer inspection technology.

Conclusion

John Fretwell's contributions to wafer defect inspection demonstrate his commitment to innovation in the semiconductor industry. His patented methods are paving the way for improved quality control and defect characterization.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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