Tianjin, China

Jiyong Niu

This inventor holds 2 USPTO granted patents and 1 published patent application. Top assignee: Freescale Semiconductor,inc.. Active years: 2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jiyong Niu. Retrieved from https://idiyas.com/inventor/jiyong-niu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 2 

% Patents Active = 50.0

Average Co-Inventor Count = 5.5

ph-index = 1

Forward Citations = 13(Granted Patents)


Company Filing History:


Years Active: 2016

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2 patents (USPTO):Explore Patents

Title: The Innovative Journey of Jiyong Niu

Introduction: Jiyong Niu, an accomplished inventor based in Tianjin, China, has made significant contributions to the field of semiconductor technology. With a total of two patents to his name, his innovations reflect a deep understanding of the complexities involved in the semiconductor singulation process, addressing critical challenges faced in the industry.

Latest Patents: Jiyong Niu's latest patents include advanced solutions designed to enhance efficiency and reliability in semiconductor manufacturing. The first patent describes a cleaning mechanism for semiconductor singulation saws, featuring a subsystem that adeptly removes unwanted material, such as glaze, from saw blades used in the singulation process. This cleaning module is engineered to move radially towards the saw blade and vertically within the plane of the saw blade, allowing abrasive cleaning blocks to selectively target material on the upper and lower surfaces or the outer edge of the blade. This innovation not only optimizes the cleaning process but also operates at predetermined times or positions or in response to load imbalances detected during blade rotation.

His second patent involves a die edge seal employing low-K dielectric material. This technology encompasses a semiconductor wafer with multi-stage structures that effectively dampen and contain nascent cracks generated during dicing, while also preventing moisture penetration into the active regions of the die. The wafer consists of an array of die regions separated by scribe lanes, featuring an active region and a first ring surrounding it composed of low-K dielectric material. Additionally, a second ring integrates a stacked configuration of metal and interlayer dielectric materials to further enhance durability and performance.

Career Highlights: Throughout his career, Jiyong has made valuable contributions to renowned companies such as Freescale Semiconductor, Inc. His experience has not only enriched his skill set but also allowed him to stay at the forefront of semiconductor innovation.

Collaborations: Jiyong has collaborated with notable industry professionals, including Zhijie Wang and Zhigang Bai. These partnerships highlight the collaborative nature of innovation in the field, as sharing knowledge with peers enhances the potential for groundbreaking inventions.

Conclusion: Jiyong Niu exemplifies the spirit of innovation in the semiconductor industry. With his two impactful patents and collaborative work with esteemed colleagues, he continues to contribute to advancements that promise to simplify and improve the processes within semiconductor manufacturing. His journey reflects the ongoing quest for excellence and the relentless pursuit of new solutions within the technological landscape.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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