The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2016
Filed:
Nov. 26, 2014
Zhijie Wang, Tianjin, CN;
Zhigang Bai, Tianjin, CN;
Jiyong Niu, Tianjin, CN;
Dehong YE, Tianjin, CN;
Huchang Zhang, Tianjin, CN;
Zhijie Wang, Tianjin, CN;
Zhigang Bai, Tianjin, CN;
Jiyong Niu, Tianjin, CN;
Dehong Ye, Tianjin, CN;
Huchang Zhang, Tianjin, CN;
FREESCALE SEMICONDCUTOR, INC., Austin, TX (US);
Abstract
A semiconductor wafer has a multi-stage structure that damps and contains nascent cracks generated during dicing and inhibits moisture penetration into the active region of a die. The wafer includes an array of die regions separated by scribe lanes. The die regions include an active region and a first ring that surrounds the active region. A portion of the first ring includes a low-k dielectric material. A second ring includes a stack of alternating layers of metal and interlayer dielectric (ILD) material. A dummy metal region around the rings includes a stacked dummy metal features and surrounds the active region. A regular or irregular staggered arrangement of saw grid process control (SGPC) features reduces mechanical stress during dicing.