Taipei, Taiwan

Jiun-Nan Chen

This inventor holds 3 USPTO granted patents. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2004-2005.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jiun-Nan Chen. Retrieved from https://idiyas.com/inventor/jiun-nan-chen-ukzeptzb

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 33.3

Average Co-Inventor Count = 2.0

ph-index = 3

Forward Citations = 24(Granted Patents)


Location History:

  • Hsin-Chu, TW (2004)
  • Taipei, TW (2004 - 2005)

Company Filing History:


Years Active: 2004-2005

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3 patents (USPTO):Explore Patents

Title: Jiun-Nan Chen: Innovator in Semiconductor Technology

Introduction

Jiun-Nan Chen is a prominent inventor based in Taipei, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 3 patents. His innovative methods have advanced the manufacturing processes of semiconductor devices, particularly in the areas of electron charging and ROM product fabrication.

Latest Patents

One of Jiun-Nan Chen's latest patents is a method to monitor the process charging effect. This new method provides a way to monitor the effect of electron charging during the creation of a semiconductor device. It utilizes electron trapping that occurs as a result of Fowler-Nordheim (FN) tunneling in a layer of interlayer oxide of an EEPROM device. The method allows for monitoring under processing conditions, and after electron trapping occurs, the rate of discharge of the trapped electron charge is measured during Wafer Acceptance Testing (WAT).

Another significant patent involves products derived from embedded flash/EEPROM products. This patent discloses a method of fabricating ROM products through the use of embedded flash/EEPROM prototypes. The process begins with forming a Flash/EEPROM prototype, performing programming simulations, developing a ROM code and mask, and then forming a ROM product in the same manufacturing line. This method improves turnaround time in the manufacturing line and reduces costs for customers.

Career Highlights

Jiun-Nan Chen is currently employed at Taiwan Semiconductor Manufacturing Company Limited, where he continues to innovate and contribute to the semiconductor industry. His work has not only enhanced manufacturing efficiency but has also provided valuable solutions to common challenges faced in the field.

Collaborations

Throughout his career, Jiun-Nan has collaborated with notable colleagues, including Kuei-Ying Lee and Shao-Yu Chou. These collaborations have fostered a creative environment that encourages the development of groundbreaking technologies.

Conclusion

Jiun-Nan Chen's contributions to semiconductor technology through his patents and innovative methods have made a lasting impact on the industry. His work exemplifies the spirit of innovation that drives advancements in technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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