Chengdu, China

Jie Wei

This inventor holds 2 USPTO granted patents. Top assignee: University of Electronic Science and Technology of China. Active years: 2016-2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jie Wei. Retrieved from https://idiyas.com/inventor/jie-wei-m6c8g0pb

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 7.0

ph-index = 1

Forward Citations = 8(Granted Patents)


Company Filing History:


Years Active: 2016-2019

Loading Chart...
2 patents (USPTO):Explore Patents

Title: Innovations of Jie Wei in Semiconductor Technology

Introduction

Jie Wei is a prominent inventor based in Chengdu, China, known for his contributions to semiconductor technology. He holds 2 patents that showcase his innovative approach to enhancing electronic devices.

Latest Patents

One of Jie Wei's latest patents is titled "Polarization-doped enhancement mode HEMT." This invention pertains to semiconductor technology and involves a polarization-doped enhancement mode HEMT device. The technical solution includes the sequential growth of the first and second barrier layers with gradient Al composition on a buffer layer. The gradient trends of these layers are opposite, leading to the generation of three-dimensional electron gas (3DEG) and three-dimensional hole gas (3DHG) in the barrier layers due to inner polarization differences. A trench insulated gate structure is positioned away from the metal drain and in contact with the source, significantly improving the on-state current due to the presence of highly concentrated electrons in the first barrier layer. Additionally, the vertical conductive channel between the source and the 3DEG is pinched off by the 3DHG, achieving the enhancement mode.

Another significant patent is the "Enhancement mode high electron mobility transistor." This invention includes a substrate layer, buffer layer, barrier layers, drain electrodes, reverse polarization semiconductor layers, source electrodes, an insulated gate dielectric, and a metal gate electrode. The buffer layer is placed on the substrate layer, with barrier layers on top. The interfaces between the buffer layer and barrier layers feature first heterojunctions that create a two-dimensional electron gas (2DEG) channel. The drain electrodes are located at one end of the upper surfaces of the barrier layers, forming Ohmic contact. The reverse polarization semiconductor layers on the barrier layers produce inversed polarization, with second heterojunctions providing a two-dimensional hole gas (2DHG).

Career Highlights

Jie Wei is affiliated with the University of Electronic Science and Technology of China, where he continues to advance research in semiconductor technologies. His work has significantly impacted the field, particularly in enhancing the performance of electronic devices.

Collaborations

Jie Wei collaborates with notable colleagues, including Fu Peng and Xiaorong Luo, contributing to various research projects and innovations in semiconductor technology.

Conclusion

Jie Wei's innovative patents and contributions to semiconductor technology highlight his role as

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…