Union City, CA, United States of America

Jie Liu

This inventor holds 2 USPTO granted patents and 1 published patent application. Top assignee: Lam Research Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jie Liu. Retrieved from https://idiyas.com/inventor/jie-liu-60v7xex5

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 2 

Average Co-Inventor Count = 9.0

ph-index = 1


Company Filing History:


Years Active: 2026

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2 patents (USPTO):Explore Patents

Title: Jie Liu - Innovator in Substrate Processing Technology

Introduction

Jie Liu is a notable inventor based in Union City, CA (US). He has made significant contributions to the field of substrate processing technology. His innovative work has led to the development of a unique patent that enhances the efficiency of processing chambers.

Latest Patents

Jie Liu holds a patent for a Flat Bottom Shadow Ring (fBSR). This invention is designed for processing a substrate in a processing chamber. The fBSR features an overhang that covers the edge of the substrate, which includes a flat zone extending radially outward over the outer edge of the substrate. This design aims to improve the processing conditions within the chamber.

Career Highlights

Jie Liu is currently employed at Lam Research Corporation, a leading company in semiconductor manufacturing equipment. His role at the company allows him to apply his expertise in substrate processing and contribute to advancements in the industry.

Collaborations

Jie Liu has collaborated with talented coworkers, including Lai Wei and Ji Soo Kim. Their combined efforts in research and development have fostered innovation within their projects.

Conclusion

Jie Liu's contributions to substrate processing technology through his patent and work at Lam Research Corporation highlight his role as an influential inventor in the field. His innovative spirit continues to drive advancements in semiconductor manufacturing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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