Jianliang Shen

Title: Innovations of Jianliang Shen in Wafer-Level Integration

Introduction

Jianliang Shen is a prominent inventor based in Hangzhou, China. He has made significant contributions to the field of semiconductor technology, particularly in wafer-level integration. With a total of three patents to his name, Shen's work focuses on enhancing the efficiency and yield of integrated circuits.

Latest Patents

Shen's latest patents include a "Routing structure and method of wafer substrate with standard integration zone for integration on-wafer." This invention addresses the yield problem associated with wafer substrates that have few metal layers. It features a core voltage network, an interconnection signal network, a clock signal network, and a ground network, all designed to optimize the integration process. Another notable patent is the "Wafer-level heterogeneous dies integration structure and method." This patent outlines a structure that includes a wafer substrate, silicon interposer, heterogeneous dies, and a configuration substrate, facilitating efficient integration of various components.

Career Highlights

Jianliang Shen is currently employed at Zhejiang Lab, where he continues to innovate in the field of semiconductor technology. His work has been instrumental in advancing the capabilities of wafer-level integration, making significant strides in the industry.

Collaborations

Shen collaborates with notable colleagues such as Weihao Wang and Shunbin Li, contributing to a dynamic research environment that fosters innovation and development.

Conclusion

Jianliang Shen's contributions to wafer-level integration technology are noteworthy and impactful. His patents reflect a deep understanding of semiconductor design and integration, positioning him as a key figure in the field.