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For the Inventor, By the Inventor

Austin, TX, United States of America

Jhih-Rong Gao

USPTO Granted Patents = 11

Average Co-Inventor Count = 3.4

ph-index = 3

Forward Citations = 17(Granted Patents)


Company Filing History:

goldMedal11 out of 2,542 
 
Cadence Design Systems, Inc.
 patents

Years Active: 2018-2024

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11 patents (USPTO):
1. 11868695 - Driver resizing using a transition-based pin capacitance increase margin (2024-01-09),
2. 11675956 - Pruning redundant buffering solutions using fast timing models (2023-06-13),
3. 11526650 - Switching power aware driver resizing by considering net activity in buffering algorithm (2022-12-13),
4. 11520959 - Pruning of buffering candidates for improved efficiency of evaluation (2022-12-06),
5. 11514222 - Cell-width aware buffer insertion technique for narrow channels (2022-11-29),
6. 11347923 - Buffering algorithm with maximum cost constraint (2022-05-31),
7. 10963620 - Buffer insertion technique to consider edge spacing and stack via design rules (2021-03-30),
8. 10936777 - Unified improvement scoring calculation for rebuffering an integrated circuit design (2021-03-02),
9. 10860764 - Layer assignment technique to improve timing in integrated circuit design (2020-12-08),
10. 10289795 - Routing tree topology generation (2019-05-14),
11. 10031994 - Systems and methods for congestion and routability aware detailed placement (2018-07-24),

Title: Jhih-Rong Gao: Innovator in Integrated Circuit Design

Introduction

Jhih-Rong Gao is a prominent inventor based in Austin, TX, known for his significant contributions to integrated circuit design. With a total of 11 patents to his name, he has made remarkable advancements in the field of electronics and circuit optimization.

Latest Patents

One of his latest patents is titled "Driver resizing using a transition-based pin capacitance increase margin." This patent addresses systems and methods for driver resizing by determining a capacitance increase margin based on the total capacitance of a net and the transition time target associated with an initial driver cell. The process involves selecting an alternative driver cell from a library to replace the initial driver cell while ensuring that the pin capacitance of the alternative driver does not exceed the capacitance increase margin.

Another notable patent is "Pruning redundant buffering solutions using fast timing models." This invention includes a system that accesses an integrated circuit design with a buffer tree. The operations involve identifying candidate solutions for improving the baseline timing characteristic and selecting a subset of these solutions for evaluation. The goal is to update the buffer tree based on the selected candidate solution that offers a better timing characteristic than the baseline.

Career Highlights

Jhih-Rong Gao is currently employed at Cadence Design Systems, Inc., where he continues to innovate and develop cutting-edge solutions in integrated circuit design. His work has significantly impacted the efficiency and performance of electronic systems.

Collaborations

Throughout his career, Jhih-Rong has collaborated with talented individuals such as Zhuo Li and Yi-Xiao Ding. These collaborations have fostered a creative environment that has led to the development of advanced technologies in the field.

Conclusion

Jhih-Rong Gao's contributions to integrated circuit design through his innovative patents and collaborations highlight his role as a leading inventor in the electronics industry. His work continues to influence the future of circuit design and optimization.

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