The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 30, 2021
Filed:
Jan. 06, 2020
Cadence Design Systems, Inc., San Jose, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Aspects of the present disclosure address improved systems and methods for buffer insertion in an integrated circuit (IC) design using a cost function that accounts for edge spacing and stack via constraints associated with cells in the IC design. An integrated circuit (IC) design comprising a routing topology for a net is accessed. A set of candidate insertion locations along the routing topology are identified. A set of buffering candidates is generated based on the candidate insertion locations. A buffering candidate comprises a cell inserted at a candidate insertion location along the routing topology. A cost associated with the buffering candidate is determined based on a number of potential edge spacing conflicts and a number of stack vias associated with the cell. A buffering solution for the net is selected from the buffering candidate based on the cost associated with the buffering candidate.