Lans en Vercors, France

Jerome Teysseyre

This inventor holds 1 USPTO granted patent. Top assignee: STMicroelectronics. Active years: 2008.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jerome Teysseyre. Retrieved from https://idiyas.com/inventor/jerome-teysseyre-houtwseq

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2008

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1 patent (USPTO):Explore Patents

Title: Jerome Teysseyre: Semiconductor Packaging Inventor

Introduction

Jerome Teysseyre is an inventor associated with Lans-en-Vercors, France, and STMicroelectronics. His patent work concerns semiconductor packaging and leadframe design.

Latest Patents

Teysseyre is named on one patent, titled “Process for Fabricating a Semiconductor Package and Semiconductor Package with Leadframe.” The invention describes a flat metal leadframe with spaced-apart portions, some of which serve as electrical connection leads. Filling material occupies the spaces between those portions to form a plate. An integrated circuit chip is then attached to the leadframe, electrically connected to the leads, and encapsulated on the front side. Teysseyre’s record lists 1 patent.

Career Highlights

The available information associates Teysseyre with STMicroelectronics and identifies his patent contribution in semiconductor package fabrication. The described approach integrates leadframe preparation, chip attachment, electrical connections, and encapsulation into a package structure.

Collaborations

Jean-Luc Diot is identified as Teysseyre’s coworker. The supplied information does not specify whether Diot collaborated on this patent.

Conclusion

Jerome Teysseyre’s documented invention addresses the fabrication of semiconductor packages using a filled leadframe, highlighting his contribution to packaging technology at STMicroelectronics.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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