O'Fallon, MO, United States of America

Jeffrey L Libbert

This inventor holds 1 USPTO granted patent and 7 published patent applications and 1 EPO patent. Top assignee: Globalwafers Co., Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jeffrey L Libbert. Retrieved from https://idiyas.com/inventor/jeffrey-l-libbert

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

% Patents Active = 100.0

 

Average Co-Inventor Count = 3.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Jeffrey L. Libbert: Semiconductor Wafer Manufacturing Innovation

Introduction

Jeffrey L. Libbert is an inventor associated with O’Fallon, Missouri, and GlobalWafers Co., Ltd. His patent work concerns methods for manufacturing semiconductor-on-insulator wafers, with particular attention to controlling stress in charge-trapping layers.

Latest Patents

Libbert is named on one patent: “Methods of Manufacturing Semiconductor-on-Insulator Wafers Having Charge Trapping Layers with Controlled Stress.” The disclosed method prepares a multilayer structure using a single-crystal semiconductor handle substrate with a minimum bulk-region resistivity of at least about 500 ohm-centimeters. It deposits a semiconductor layer on the substrate through two or more cycles, interrupting deposition after each portion so that the deposited material can be annealed.

Career Highlights

The patent reflects Libbert’s contribution to semiconductor wafer manufacturing processes. Its approach combines controlled deposition and intermediate annealing to address stress in multilayer wafer structures.

Collaborations

Libbert’s listed coworkers include Charles R. Lottes and Qingmin Liu. The patent identifies their work in the context of semiconductor-on-insulator wafer manufacturing.

Conclusion

Jeffrey L. Libbert’s recorded patent contribution focuses on a staged deposition and annealing method for preparing semiconductor wafers with controlled stress, and his patent portfolio includes 1 patent.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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