Jeena Mary George

Title: Jeena Mary George: Innovator in Digital Circuit Testing

Introduction

Jeena Mary George is a notable inventor based in Kattappana, India. He has made significant contributions to the field of digital circuit testing, holding three patents that showcase his innovative approach to improving circuit reliability and efficiency.

Latest Patents

One of his latest patents focuses on "Test time reduction in circuits with redundancy flip-flops." This invention provides a digital circuit with a number of redundant flip-flops, each connected to a common data signal. The circuit operates in both functional and test modes, allowing for effective fault detection during testing. Another significant patent is titled "TVF transition coverage with self-test and production-test time reduction." This method enhances the testing of triple-voting flops (TVFs) by utilizing multiple scan enable signals to ensure thorough fault detection.

Career Highlights

Jeena Mary George is currently employed at STMicroelectronics International N.V., where he applies his expertise in digital circuit design and testing. His work has been instrumental in advancing the reliability of electronic components.

Collaborations

He has collaborated with notable coworkers, including Sandeep Jain and Akshay Kumar Jain, contributing to various projects that enhance circuit testing methodologies.

Conclusion

Jeena Mary George's innovative patents and contributions to digital circuit testing reflect his commitment to advancing technology in the electronics industry. His work continues to influence the field, ensuring greater reliability in electronic devices.