This inventor holds 1 USPTO granted patent. Top assignee: Synopsys, Inc.. Active years: 2013.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2013
Title: Innovations by Jean-Christophe Madre in Circuit Design
Introduction
Jean-Christophe Madre is a notable inventor based in Grenoble, France. He has made significant contributions to the field of circuit design, particularly in optimizing delay during the layout phase. His work is essential for enhancing the efficiency of integrated circuit fabrication.
Latest Patents
Jean-Christophe Madre holds a patent for "Delay optimization during circuit design at layout level." This patent describes a method of designing a circuit layout and corresponding computer systems and nontransitory computer media. The circuit layout is intended for use in forming a lithographic mask set for fabricating an integrated circuit. The method involves dividing a synthesized circuit design into cell partitions along critical paths. It also associates pins of these cell partitions with normalized pin timing values, which store magnitude differences between a reference timing slack and the timing slacks of the pins. After optimizing the synthesized circuit design, the method is repeated to determine if further optimization is necessary by comparing pre- and post-optimization normalized pin timing values.
Career Highlights
Jean-Christophe Madre is currently employed at Synopsys, Inc., where he continues to innovate in the field of circuit design. His expertise in optimizing circuit layouts has positioned him as a valuable asset in the industry.
Collaborations
One of his notable coworkers is Patrick Vuillod, with whom he collaborates on various projects related to circuit design and optimization.
Conclusion
Jean-Christophe Madre's contributions to circuit design through his innovative patent demonstrate his commitment to advancing technology in this field. His work continues to influence the efficiency of integrated circuit fabrication processes.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
