Delay optimization during circuit design at layout level

Abstract

Aspect of the technology are a method of designing a circuit layout and corresponding computer systems and nontransitory computer media. The circuit layout is for use in forming a lithographic mask set for use in fabricating an integrated circuit. In the method the computer system divides a synthesized circuit design into cell partitions along critical paths of the synthesized circuit design. The computer system associates pins of the plurality of cell partitions with normalized pin timing values. The normalized pin timing values store magnitude differences between a reference timing slack and timing slacks of the plurality of pins. After optimizing the synthesized circuit design, the computer system repeats the method, and then the computer system determines whether to further optimize the plurality of cell partitions by comparing: (i) the pre-optimization normalized pin timing values of the plurality of cell partitions with (ii) the post-optimization normalized pin timing values of the plurality of cell partitions.