Jaydev Amit Shelat

Title: Jaydev Amit Shelat: Innovator in Delay Test Circuitry

Introduction

Jaydev Amit Shelat is a notable inventor based in Santa Clara, CA (US). He has made significant contributions to the field of integrated circuits, particularly in the area of delay test circuitry. His innovative work has led to the development of a patent that enhances the testing capabilities of circuits under test.

Latest Patents

Jaydev holds a patent for "Delay Test Circuitry." This programmable delay test circuitry is designed for testing a circuit under test on an integrated circuit. The circuitry utilizes logic to output an error signal when the delay time provided by the circuit under test exceeds a characteristic time that can be programmed into the delay test circuitry. The design includes a logic gate that generates a pulse with a width equal to the delay of the circuitry. Additionally, it features a programmable load that can be set to a specific characteristic time, asserting an error signal when the delay time surpasses this programmed characteristic time. Jaydev has 1 patent to his name.

Career Highlights

Jaydev Amit Shelat is currently employed at Altera Corporation, where he continues to innovate and contribute to advancements in integrated circuit technology. His work at Altera has positioned him as a key player in the development of cutting-edge testing solutions.

Collaborations

Throughout his career, Jaydev has collaborated with talented individuals such as Zunhang Yu Kasnavi and Dhananjay Srinivasa Raghavan. These collaborations have fostered an environment of innovation and creativity, leading to significant advancements in their respective fields.

Conclusion

Jaydev Amit Shelat is a distinguished inventor whose work in delay test circuitry has made a lasting impact on the field of integrated circuits. His contributions continue to influence the way circuits are tested and validated, showcasing the importance of innovation in technology.