The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2013
Filed:
Feb. 03, 2009
Jaydev Amit Shelat, Santa Clara, CA (US);
Zunhang Yu Kasnavi, Sunnyvale, CA (US);
Dhananjay Srinivasa Raghavan, Campbell, CA (US);
Jaydev Amit Shelat, Santa Clara, CA (US);
Zunhang Yu Kasnavi, Sunnyvale, CA (US);
Dhananjay Srinivasa Raghavan, Campbell, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Programmable delay test circuitry is provided for testing a circuit under test on an integrated circuit. Delay test circuitry may use logic circuitry to output an error signal when a delay time provided by the circuit under test is greater than a characteristic time that may be programmed into the programmable delay test circuitry. Programmable delay test circuitry may use a logic gate to provide a pulse that has a pulse width equal to the delay of the delay circuitry. Programmable delay test circuitry may contain a programmable load that may be programmed to have a characteristic time. Programmable delay test circuitry may assert an error signal when the delay time is greater than the characteristic time of the test circuitry.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile