Altera Corporation

Jaydev Amit Shelat

Zunhang Yu Kasnavi

Dhananjay Srinivasa Raghavan

Programmable delay test circuitry is provided for testing a circuit under test on an integrated circuit. Delay test circuitry may use logic circuitry to output an error signal when a delay time provided by the circuit under test is greater than a characteristic time that may be programmed into the programmable delay test circuitry. Programmable delay test circuitry may use a logic gate to provide a pulse that has a pulse width equal to the delay of the delay circuitry. Programmable delay test circuitry may contain a programmable load that may be programmed to have a characteristic time. Programmable delay test circuitry may assert an error signal when the delay time is greater than the characteristic time of the test circuitry.

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Santa Clara, CA, United States of America

Jaydev Amit Shelat