Jasmeet Singh Narula

Title: Jasmeet Singh Narula: Innovator in Electronic Design Verification

Introduction

Jasmeet Singh Narula is a notable inventor based in Delhi, India. He has made significant contributions to the field of electronic design verification. His innovative work has led to the development of a unique patent that addresses challenges in this area.

Latest Patents

Jasmeet Singh Narula holds a patent titled "System, method, and computer program product for analyzing X-propagation failures in formal verification." This patent describes a computer-implemented method for electronic design verification. The method includes receiving an electronic design at a verification environment and generating a symbolic constant for use with the verification environment. It also involves identifying a plurality of X sources associated with the verification environment and modifying these sources based on the symbolic constant. Furthermore, the method includes running a first target node and, if proven, running additional target nodes until all are verified. This innovative approach enhances the efficiency and accuracy of electronic design verification processes.

Career Highlights

Jasmeet is currently employed at Cadence Design Systems, Inc., where he continues to advance his work in electronic design automation. His expertise in this field has positioned him as a valuable asset to his company and the industry at large.

Collaborations

Throughout his career, Jasmeet has collaborated with talented professionals, including Pradeep Goyal and Deepak Yadav. These collaborations have fostered a creative environment that encourages innovation and problem-solving.

Conclusion

Jasmeet Singh Narula is a distinguished inventor whose work in electronic design verification has made a significant impact. His patent demonstrates his commitment to advancing technology in this field. His contributions continue to influence the landscape of electronic design automation.