Jaskaran Singh Ajimal

Title: Jaskaran Singh Ajimal: Innovator in RTL Code Verification

Introduction

Jaskaran Singh Ajimal is a notable inventor based in San Jose, CA (US). He has made significant contributions to the field of verification complexity in RTL code. His innovative approach aims to enhance the performance of equivalence checkers, which are crucial in the verification process of digital designs.

Latest Patents

Jaskaran holds a patent for his work titled "Identifying RTL code that can be a source of verification complexity for downstream equivalence checkers and generating recommendations to improve runtime of equivalence checkers." This patent focuses on improving the runtime performance of equivalence checkers through a shift left process. By utilizing an RTL lint tool, he identifies RTL code that may contribute to verification complexity. The RTL code is then compared to a corresponding circuit model to pinpoint potential gate-level locations of problematic code. A weight is calculated to represent the level of verification complexity generated by specific portions of the RTL code. Additionally, the RTL lint tool generates recommendations to mitigate verification complexity for downstream equivalence checkers. Jaskaran has 1 patent to his name.

Career Highlights

Jaskaran is currently employed at Synopsys, Inc., a leading company in electronic design automation. His work at Synopsys involves collaborating with other experts in the field to advance verification methodologies and improve design efficiency.

Collaborations

One of his notable coworkers is Himanshu Kathuria. Together, they contribute to the innovative projects at Synopsys, focusing on enhancing the verification processes in digital design.

Conclusion

Jaskaran Singh Ajimal is a prominent inventor whose work in RTL code verification is paving the way for improved methodologies in the field. His contributions are essential for advancing the efficiency of equivalence checkers in digital design verification.