The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2026

Filed:

Mar. 24, 2023
Applicant:

Synopsys, Inc., Sunnyvale, CA (US);

Inventors:

Himanshu Kathuria, Fremont, CA (US);

Makarand Patil, Portland, OR (US);

Rohit Kumar Ohlayan, New Delhi, IN;

Paras Mal Jain, Mountain View, CA (US);

Ila Verma, Rajpura, IN;

Mohan Mangal, Fremont, CA (US);

Jaideep Dutt, Carrollton, TX (US);

Jaskaran Singh Ajimal, San Jose, CA (US);

Harpreet Singh Anand, Nagar, IN;

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/327 (2020.01);
U.S. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/327 (2020.01);
Abstract

Aspects of the present disclosure relate to improving runtime performance of equivalence checkers by a shift left process that uses an RTL lint tool to identify RTL code that can be a source of verification complexity for the downstream equivalence checker. The RTL code is further compared to a corresponding circuit model to determine a potential gate-level location of the potentially problematic RTL code. A weight can be calculated to represent a level of verification complexity that may be generated by the particular portion of the RTL code. Further, one or more recommendations can be generated by the RTL lint tool to prevent some of the verification complexity for the downstream equivalence checker.


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