IDiyas

For the Inventor, By the Inventor

Campbell, CA, United States of America

Jangseok Choi

USPTO Granted Patents = 24 

Average Co-Inventor Count = 5.2

ph-index = 4

Forward Citations = 56(Granted Patents)


Location History:

  • Seoul, KR (2012)
  • Hwasung, KR (2019)
  • Hwasung-Si, KR (2019 - 2021)
  • Suwon-si, KR (2021 - 2022)
  • Campbell, CA (US) (2019 - 2023)
  • Seongnam-si, KR (2021 - 2023)
  • San Jose, CA (US) (2017 - 2024)

Company Filing History:

goldMedal24 out of 131,214 
 
Samsung Electronics Co., Ltd.
 patents

Years Active: 2012-2025

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24 patents (USPTO):
1. 12468445 - Coordinated in-module RAS features for synchronous DDR compatible memory (2025-11-11),
2. 12242344 - DRAM assist error correction mechanism for DDR SDRAM interface (2025-03-04),
3. 12189546 - Asynchronous communication protocol compatible with synchronous DDR protocol (2025-01-07),
4. 12032828 - Coordinated in-module RAS features for synchronous DDR compatible memory (2024-07-09),
5. 11756646 - Memory module with reduced ECC overhead and memory system (2023-09-12),
6. 11625296 - DRAM assist error correction mechanism for DDR SDRAM interface (2023-04-11),
7. 11507456 - Memory module, error correction method of memory controller controlling the same, and computing system including the same (2022-11-22),
8. 11397698 - Asynchronous communication protocol compatible with synchronous DDR protocol (2022-07-26),
9. 11294571 - Coordinated in-module RAS features for synchronous DDR compatible memory (2022-04-05),
10. 11222709 - Memory module with reduced ECC overhead and memory system (2022-01-11),
11. 11157358 - Memory module, error correction method of memory controller controlling the same, and computing system including the same (2021-10-26),
12. 11068347 - Memory controllers, memory systems including the same and memory modules (2021-07-20),
13. 11010242 - DRAM assist error correction mechanism for DDR SDRAM interface (2021-05-18),
14. 10977118 - DRAM assist error correction mechanism for DDR SDRAM interface (2021-04-13),
15. 10908993 - Method to deliver in-DRAM ECC information through DDR bus (2021-02-02),

Title: Innovations by Jangseok Choi in Memory Technology

Introduction

Jangseok Choi is an accomplished inventor based in Campbell, California, known for his significant contributions to the field of memory technology. With a remarkable portfolio of 23 patents, Choi has played a pivotal role in advancing dynamic random-access memory (DRAM) systems. His innovative work has had a lasting impact on memory interfaces and error correction mechanisms used in various electronic devices.

Latest Patents

Among his latest inventions, Choi has developed a **DRAM assist error correction mechanism for DDR SDRAM interface**. This method outlines a sophisticated process for correcting memory errors in dynamic random-access memory modules by employing a double data rate interface. The technique involves conducting memory transactions, detecting errors with an ECC chip, and analyzing the data to enhance memory reliability.

Additionally, Choi's invention titled **Asynchronous communication protocol compatible with synchronous DDR protocol** introduces a novel memory module featuring a non-volatile memory and an asynchronous memory interface. This design cleverly repurposes pins of a DDR memory channel to facilitate asynchronous data transmission to the memory controller, providing vital device feedback.

Career Highlights

Choi works at Samsung Electronics Co., Ltd., one of the leading companies in the electronics sector. His career at Samsung has been marked by groundbreaking innovations in memory technology, further solidifying his status as a leading inventor in the field. His 23 patents demonstrate his deep commitment to improving memory efficiency and performance.

Collaborations

Throughout his career, Jangseok Choi has collaborated with other talented professionals such as Dimin Niu and Mu-Tien Chang. These collaborations have led to numerous advancements in memory technologies, enhancing the overall capabilities of the projects they have worked on together.

Conclusion

Jangseok Choi continues to be an influential figure in the realm of memory technology. With his extensive patent portfolio and groundbreaking innovations, he is paving the way for future developments in DRAM interfaces and error correction methodologies. His contributions not only enhance the performance of current technologies but also lay the groundwork for future innovations in the field.

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