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For the Inventor, By the Inventor

Austin, TX, United States of America

James David Barnette

This inventor holds 21 USPTO granted patents and 2 published patent applications. Top assignees: Silicon Laboratories Inc., Skyworks Solutions, Inc., Lucent Technologies Inc.. Active years: 2000-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: James David Barnette. Retrieved from https://idiyas.com/inventor/james-david-barnette

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 21 

% Patents Active = 100.0

Average Co-Inventor Count = 2.2

ph-index = 8

Forward Citations = 368(Granted Patents)


Company Filing History:

goldMedal11 out of 1,783 
 
Silicon Laboratories Inc.
 patents
silverMedal4 out of 2,882 
 
Skyworks Solutions, Inc.
 patents
bronzeMedal2 out of 9,364 
 
Lucent Technologies Inc.
 patents
4. 2 out of 104 
 
Vitesse Semiconductor Corporation
 patents
5. 1 out of 1,310 
 
Alcatel-Lucent USA Inc.
 patents
6. 1 out of 2,683 
 
Cirrus Logic Inc.
 patents

Years Active: 2000-2026

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21 patents (USPTO):Explore Patents
1. 12519477 - Method and an apparatus for generating an output clock in a multi-loop PLL system (2026-01-06),
2. 12436504 - Using time-to-digital converters to delay signals with high accuracy and large range (2025-10-07),
3. 12019406 - Using time-to-digital converters to delay signals with high accuracy and large range (2024-06-25),
4. 11526135 - Using time-to-digital converters to delay signals with high accuracy and large range (2022-12-13),
5. 11342926 - Synchronization of clock signals generated using output dividers (2022-05-24),
6. 11245406 - Method for generation of independent clock signals from the same oscillator (2022-02-08),
7. 11038521 - Spur and quantization noise cancellation for PLLS with non-linear phase detection (2021-06-15),
8. 10951216 - Synchronization of clock signals generated using output dividers (2021-03-16),
9. 10826507 - Fractional divider with error correction (2020-11-03),
10. 10819354 - Accurate and reliable digital PLL lock indicator (2020-10-27),
11. 10727845 - Use of a virtual clock in a PLL to maintain a closed loop system (2020-07-28),
12. 10727844 - Reference clock frequency change handling in a phase-locked loop (2020-07-28),
13. 10693475 - Gradual frequency transition with a frequency step (2020-06-23),
14. 10651862 - Locking a PLL to the nearest edge of the input clock when the input clock is divided down before use in the PLL (2020-05-12),
15. 10608649 - Relative frequency offset error and phase error detection for clocks (2020-03-31),

Title: The Innovative Journey of James David Barnette

Introduction: James David Barnette, a talented inventor based in Austin, Texas, has made significant contributions to the field of technology with his creative and groundbreaking ideas.

Latest Patents: James David Barnette holds several patents in various technological fields, including artificial intelligence, renewable energy, and medical devices, showcasing his diverse range of expertise and innovative thinking.

Career Highlights: With a background in engineering and a passion for problem-solving, James David Barnette has successfully brought several inventions from concept to reality, revolutionizing industries and improving people's lives along the way.

Collaborations: Throughout his career, James David Barnette has collaborated with leading tech companies, research institutions, and universities to further develop his inventions and bring them to the market, demonstrating his ability to work effectively in multidisciplinary teams.

Conclusion: James David Barnette's relentless pursuit of innovation and his commitment to pushing the boundaries of technology make him a true visionary in the world of inventions. His impact on various industries is profound, and his legacy as an inventor continues to inspire future generations of innovators.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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