The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2022

Filed:

Jun. 30, 2020
Applicant:

Silicon Laboratories Inc., Austin, TX (US);

Inventors:

Harihara Subramanian Ranganathan, Round Rock, TX (US);

Xue-Mei Gong, Austin, TX (US);

James D. Barnette, Austin, TX (US);

Nathan J. Shashoua, Austin, TX (US);

Srisai Rao Seethamraju, Nashua, NH (US);

Assignee:

Silicon Laboratories Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/197 (2006.01); H03L 7/093 (2006.01);
U.S. Cl.
CPC ...
H03L 7/1974 (2013.01); H03L 7/093 (2013.01);
Abstract

A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment.


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