The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2020

Filed:

Nov. 19, 2018
Applicant:

Silicon Laboratories Inc., Austin, TX (US);

Inventors:

Kannanthodath V. Jayakumar, Austin, TX (US);

James David Barnette, Austin, TX (US);

Assignee:

Silicon Laboratories Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/087 (2006.01); H03L 7/18 (2006.01); H03L 7/093 (2006.01); H03L 7/089 (2006.01);
U.S. Cl.
CPC ...
H03L 7/087 (2013.01); H03L 7/0898 (2013.01); H03L 7/093 (2013.01); H03L 7/18 (2013.01);
Abstract

An apparatus for providing a clock signal based on a received clock signal includes a time-to-digital converter configured to generate timestamp information based on the received clock signal. The apparatus includes a first filter configured to generate clock period information based on the timestamp information. The apparatus includes a phase monitor circuit. The phase monitor circuit includes a second filter configured to provide a mean period signal of the received clock signal based on the clock period information. The phase monitor includes a phase error detection circuit configured to generate a phase error indicator based on a threshold difference value and a difference between the clock period information and expected clock period information. The expected clock period information is based on the mean period signal.


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