Icheon, South Korea

Jaekang Yoo

This inventor holds 1 USPTO granted patent. Top assignee: Stats Chippac Pte. Ltd.. Active years: 2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jaekang Yoo. Retrieved from https://idiyas.com/inventor/jaekang-yoo

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 6.0

ph-index = 1


Company Filing History:


Years Active: 2015

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1 patent (USPTO):Explore Patents

Title: Jaekang Yoo: Innovator in Integrated Circuit Packaging

Introduction

Jaekang Yoo is a notable inventor based in Icheon, South Korea. He has made significant contributions to the field of integrated circuit packaging. His innovative work focuses on enhancing the reliability and efficiency of electronic components.

Latest Patents

Jaekang Yoo holds a patent for an "Integrated circuit packaging system with void prevention mechanism and method of manufacture thereof." This invention includes a singulation substrate featuring an air vent portion with longitudinal grooves, which are all parallel to each other. The integrated circuit die is attached to the singulation substrate, and a molding compound is applied on the singulation substrate, covering the air vent portion, a portion of the longitudinal grooves, and the integrated circuit die. This innovative design aims to prevent voids during the manufacturing process, thereby improving the overall performance of the integrated circuit packaging.

Career Highlights

Jaekang Yoo is currently employed at Stats Chippac Pte. Ltd., where he continues to develop cutting-edge technologies in the field of integrated circuits. His work has been instrumental in advancing the capabilities of electronic devices.

Collaborations

Jaekang Yoo collaborates with talented colleagues, including Jaewon Kim and Jaepil Kim. Together, they contribute to the innovative environment at Stats Chippac Pte. Ltd.

Conclusion

Jaekang Yoo's contributions to integrated circuit packaging demonstrate his commitment to innovation and excellence in technology. His patent reflects a significant advancement in the field, showcasing his expertise and dedication to improving electronic components.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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