Hsinchu, Taiwan

Hung-Wen Chou

This inventor holds 2 USPTO granted patents and 1 published patent application. Top assignees: Silicongear Corporation, Other. Active years: 2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hung-Wen Chou. Retrieved from https://idiyas.com/inventor/hung-wen-chou-p5yabjys

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 2 

% Patents Active = 100.0

Average Co-Inventor Count = 2.4

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:


Years Active: 2017

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2 patents (USPTO):Explore Patents

Title: Innovations of Inventor Hung-Wen Chou

Introduction

Hung-Wen Chou is a notable inventor based in Hsinchu County, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 2 patents. His work focuses on advanced MOSFET designs that enhance performance and efficiency.

Latest Patents

One of his latest patents is the Split-gate MOSFET. This innovative design includes first and second epitaxial layers, first, second, and third gates, a gate oxide layer, a trench oxide layer, and a trench implantation region formed on a substrate in order. The second epitaxial layer has a doping concentration greater than that of the first epitaxial layer. A plurality of trenches is present in the first and second epitaxial layers. Both the first and second gates are located in each of the trenches in a cell region, while the third gates are located in each of the trenches in a terminal region. The third gate closest to the cell region is grounded, and the others are floating. The gate oxide layer is disposed between the first and second gates. The trench oxide layer is located between the first gate and the first epitaxial layer and between the trench surface and the third gate. The trench implantation region is located in the first epitaxial layer at the bottom of the trench and has a doping concentration less than that of the first epitaxial layer.

Another significant patent is the Adaptive duo-gate MOSFET. This design includes a trench MOSFET and an adaptive element. The trench MOSFET consists of a source, a drain, a first gate, a second gate, and a dielectric layer between the first and second gates. The first gate may generate charge-coupling in blocking operation, while the second gate may form a channel in the trench MOSFET during conduction operation. The adaptive element is electrically coupled to the first gate, the second gate, and the source respectively. When a potential difference between the second gate and the source exceeds a predetermined value, the first gate and the source are electrically disconnected, and then the first gate and the second gate are electrically connected. After a predetermined time, the first gate and the second gate are electrically disconnected, and then the first gate and the source are electrically connected.

Career Highlights

Hung-Wen Chou has worked with Silicongear Corporation,

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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