Tainan, Taiwan

Hung-Chin Lin

This inventor holds 3 USPTO granted patents. Top assignee: United Microelectronics Corp.. Active years: 2018-2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hung-Chin Lin. Retrieved from https://idiyas.com/inventor/hung-chin-lin

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 7.0

ph-index = 1

Forward Citations = 4(Granted Patents)


Company Filing History:


Years Active: 2018-2019

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3 patents (USPTO):Explore Patents

Title: Innovations of Inventor Hung-Chin Lin

Introduction

Hung-Chin Lin is a notable inventor based in Tainan, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 3 patents. His work focuses on enhancing semiconductor structures and methods for defect review.

Latest Patents

Hung-Chin Lin's latest patents include a semiconductor structure that features a wafer with multiple viewing fields. This structure defines a plurality of dies, marked by a scribe line in each viewing field. Additionally, it incorporates various mark patterns and anchor patterns, which are distinct from one another. Another patent details a method for reviewing defects in semiconductor structures, emphasizing the same innovative features as his previous work.

Career Highlights

Hung-Chin Lin is currently employed at United Microelectronics Corporation, a leading company in the semiconductor industry. His expertise and innovative approach have contributed to the advancement of semiconductor technologies.

Collaborations

He has collaborated with notable coworkers, including Yung-Teng Tsai and Chia-Chen Sun, who share a commitment to innovation in their field.

Conclusion

Hung-Chin Lin's contributions to semiconductor technology through his patents and collaborations highlight his role as a key innovator in the industry. His work continues to influence advancements in semiconductor structures and methods.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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