Hsiao Chien Lin

Title: Hsiao Chien Lin and Semiconductor Device Innovation

Introduction

Hsiao Chien Lin is an inventor based in Hsinchu, Taiwan. He is associated with Taiwan Semiconductor Manufacturing Company Limited and is listed on 2 patents.

Latest Patents

Lin’s latest patent work concerns a semiconductor device with a short-resistant capacitor plate. The disclosed device includes transistor source and drain regions in a semiconductor substrate, a gate electrode, and an adjacent isolation structure. Above the isolation structure, an inter-dielectric layer supports a capacitor film stack designed with an isolation plate covering the capacitor plate, along with a contact to the capacitor plate.

The related method describes forming the transistor and isolation structure, depositing the inter-dielectric layer and capacitor film stack, and patterning the stack to create the capacitor plate. It specifies a liquid etch process with selectivity of at least 16 relative to other materials in the capacitor film stack.

Career Highlights

Lin’s listed patent contributions focus on semiconductor device fabrication and capacitor structures. The short-resistant capacitor plate design and its manufacturing method address how the capacitor stack is patterned and etched within an integrated device.

Collaborations

Lin’s listed coworkers include Chih-Teng Liao and Cheng-Hung Tsai. His work is associated with Taiwan Semiconductor Manufacturing Company Limited.

Conclusion

Hsiao Chien Lin’s patent work highlights semiconductor fabrication techniques for forming capacitor structures with short-resistant features.