Taichung, Taiwan

Hsein-Ta Chung

This inventor holds 1 USPTO granted patent. Top assignee: United Microelectronics Corp.. Active years: 2002.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hsein-Ta Chung. Retrieved from https://idiyas.com/inventor/hsein-ta-chung

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:


Years Active: 2002

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1 patent (USPTO):Explore Patents

Title: Hsein-Ta Chung: Innovator in Semiconductor Technology

Introduction

Hsein-Ta Chung is a notable inventor based in Tai-Chung, Taiwan. He has made significant contributions to the field of semiconductor technology, particularly in the area of photo-resist layer removal.

Latest Patents

Hsein-Ta Chung holds a patent for a method of removing a photo-resist layer on a semiconductor wafer. This innovative method involves a two-step process. The first step is a dry cleaning process that injects a nitrogen-containing gas into an oxygen-free environment, utilizing a plasma reaction to remove most of the photo-resist layer. The second step is a wet cleaning process that ensures the complete removal of the photo-resist layer. He has 1 patent to his name.

Career Highlights

Hsein-Ta Chung is associated with United Microelectronics Corporation, a leading company in the semiconductor industry. His work has contributed to advancements in semiconductor manufacturing processes.

Collaborations

He has collaborated with notable colleagues, including Yi-Yu Hsu and Tong-Yu Chen, to further enhance the development of semiconductor technologies.

Conclusion

Hsein-Ta Chung's innovative methods in semiconductor technology demonstrate his commitment to advancing the field. His contributions are vital for the ongoing evolution of semiconductor manufacturing processes.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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