This inventor holds 5 USPTO granted patents. Top assignee: Vanguard International Semiconductor Corporation. Active years: 2000-2001.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2000-2001
Title: Hon-Shing Lau: Innovator in DRAM Technology
Introduction
Hon-Shing Lau is a notable inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of semiconductor technology, particularly in dynamic random-access memory (DRAM) systems. With a total of 5 patents to his name, Lau's work has advanced the efficiency and functionality of memory devices.
Latest Patents
One of Lau's latest patents is a method to test auto-refresh and self-refresh circuitry. This invention describes a method to test both auto-refresh and self-refresh of an SDRAM. The method writes a logical zero into a single cell on each word line using a write with auto-precharge and increments an internal counter with either auto-refresh or self-refresh to select the row address. The test is performed using existing circuitry on the SDRAM, and when testing self-refresh, the refresh cycle is exited shortly after a cell on a row has been written into to save test time. A test signature is formed by the logical zeros written into one cell along each word line. Comparing this signature with the expected signature provides an easy way to determine if there is a test error and where the error occurred.
Another significant patent is a power down system for regulated internal voltage supply in DRAM. This system comprises a RAS control module, self-refresh clock control circuit, and a power down control circuit. The RAS control module responds with row address strobe signals to output a first power down control signal. While all the row address strobe signals, which denote states of the memory banks, are in a first condition of inactivity, the first power down control signal will inform the power down system to turn off a regulator in the DRAM. The self-refresh clock control circuit responds with a self-refresh clock to output a second power down control signal. While the self-refresh clock is in a second condition of non-self-refresh mode, the second power down control signal will inform the power down system to turn off the regulator. The power down control circuit, coupled with the RAS control module and self-refresh clock control circuit, receives an input clock enable signal, the first power down control signal, and the third power down control signal to output a power down signal to turn off the regulator.
Career Highlights
Lau is currently employed at Vanguard International Semiconductor Corporation, where he continues to innovate in the semiconductor industry.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile