The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 08, 2001

Filed:

Oct. 28, 1999
Applicant:
Inventors:

Chuan-Cheng Hsiao, Chia-Yi Hsien, TW;

Chih-Cheng Chen, Changhua Hsien, TW;

Hon-Shing Lau, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

A semiconductor memory device with a function of equalizing voltages of dataline pair. After turning off the word line and before turning on the equalization means, the datalines are precharged and discharged to a supplied voltage and ground, respectively. Using the theory of uniform distribution of charges, the datalines are equalized into VCC/2, that is, a half of the source supply voltage. The interference on a weak voltage VCC/2 generator within the equalization means during the equalization mode is thus avoided. The equalization of voltages on the dataline pair can be achieved within a transient cycle. Complete data can thus be written or read before the next command is given.


Find Patent Forward Citations

Hsiao, Chuan-Cheng. (2001). Semiconductor memory device with function of equalizing voltage of dataline pair (U.S. Patent No. 6229744). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6229744

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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