Power down system for regulated internal voltage supply in dram

Abstract

A power down system for regulated internal power supply in DRAM comprises a RAS control module, self-refresh clock control circuit, and a power down control circuit. The RAS control module responds with row address strobe signals to output a first power down control signal. While all the row address strobe signals, which denote states of the memory banks, are in a first condition of inactivity, the first power down control signal will inform the power down system to turn off a regulator in the DRAM under the first condition. The self-refresh clock control circuit responds with a self-refresh clock to output a second power down control signal. While the self-refresh clock is in a second condition of non-self-refresh mode, the second power down control signal will inform the power down system to turn off the regulator under the second condition. The power down control circuit coupling with the ras control module and self-refresh clock control circuit receives an input clock enable signal, the first power down control signal, and the third power down control signal to output a power down signal to turn off the regulator.