Ping Tung, Taiwan

Jeng-Feng Lan

This inventor holds 2 USPTO granted patents. Top assignee: Vanguard International Semiconductor Corporation. Active years: 2000-2001.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jeng-Feng Lan. Retrieved from https://idiyas.com/inventor/jeng-feng-lan-uzc91j30

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 22(Granted Patents)


Company Filing History:


Years Active: 2000-2001

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2 patents (USPTO):Explore Patents

Title: Jeng-Feng Lan: Innovator in DRAM Technology

Introduction

Jeng-Feng Lan is a notable inventor based in Ping Tung, Taiwan. He has made significant contributions to the field of dynamic random-access memory (DRAM) technology. With a total of 2 patents, his work focuses on improving power management systems within DRAM devices.

Latest Patents

One of Jeng-Feng Lan's latest patents is a "Power down system for regulated internal voltage supply in DRAM." This innovative system includes a RAS control module, a self-refresh clock control circuit, and a power down control circuit. The RAS control module responds to row address strobe signals to output a first power down control signal. When all row address strobe signals indicate inactivity, this signal instructs the power down system to deactivate the regulator in the DRAM. The self-refresh clock control circuit generates a second power down control signal, which also informs the power down system to turn off the regulator under specific conditions. The power down control circuit integrates these components to effectively manage the power supply.

Another significant patent is the "Power down scheme for regulated sense amplifier power in DRAM." This scheme ensures that the power-supply level voltage for the sense amplifier is activated only during a designated time frame, independent of the word line turn-on time. It employs control logic gates and time delay circuits, which are triggered by internal control signals to produce a power-down control signal for the bit line sense amplifier.

Career Highlights

Jeng-Feng Lan is currently employed at Vanguard International Semiconductor Corporation, where he continues to develop innovative solutions in semiconductor technology. His expertise in power management systems has positioned him as a key contributor to advancements in DRAM technology.

Collaborations

Throughout his career, Jeng-Feng Lan has collaborated with esteemed colleagues, including Hon-Shing Lau and Jr-Houng Lu. These partnerships have fostered a collaborative environment that enhances innovation and drives technological advancements.

Conclusion

Jeng-Feng Lan's contributions to DRAM technology through his patents and collaborations highlight his role as a significant inventor in the field. His work continues to influence the development of more efficient power management systems in semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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