logo

For the Inventor, By the Inventor

Kanagawa, Japan

Hiroyuki Nakajima

This inventor holds 12 USPTO granted patents and 1 published patent application. Top assignees: Nec Electronics Corporation, Renesas Electronics Corporation, Fujitsu Corporation. Active years: 2003-2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hiroyuki Nakajima. Retrieved from https://idiyas.com/inventor/hiroyuki-nakajima

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 12 

% Patents Active = 58.3

Average Co-Inventor Count = 1.2

ph-index = 3

Forward Citations = 26(Granted Patents)


Location History:

  • Kawasaki, JP (2003 - 2014)
  • Kanagawa, JP (2006 - 2014)
  • Toyko, JP (2018)

Company Filing History:

goldMedal5 out of 2,467 
 
Nec Electronics Corporation
 patents
silverMedal5 out of 7,654 
 
Renesas Electronics Corporation
 patents
bronzeMedal1 out of 39,374 
 
Fujitsu Corporation
 patents
4. 1 out of 36,684 
 
Nec Corporation
 patents

Years Active: 2003-2018

Loading Chart...
12 patents (USPTO):Explore Patents
1. 10037063 - Semiconductor integrated circuit including a system controlling circuit (2018-07-31),
2. 8880846 - Semiconductor device (2014-11-04),
3. 8732493 - Semiconductor integrated circuit (2014-05-20),
4. 8621262 - Semiconductor integrated circuit and method for controlling semiconductor integrated circuit (2013-12-31),
5. 8055882 - Multiplexing commands from processors to tightly coupled coprocessor upon state based arbitration for coprocessor resources (2011-11-08),
6. 7536534 - Processor capable of being switched among a plurality of operating modes, and method of designing said processor (2009-05-19),
7. 7484186 - Method for designing a system LSI (2009-01-27),
8. 7478351 - Designing system and method for designing a system LSI (2009-01-13),
9. 7124311 - Method for controlling processor in active/standby mode by third decoder based on instructions sent to a first decoder and the third decoder (2006-10-17),
10. 7065719 - Method for designing a system LSI (2006-06-20),
11. 7062724 - Method for designing a system LSI (2006-06-13),
12. 6627094 - Method of manufacturing thin film head (2003-09-30),
Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…