Method for controlling processor in active/standby mode by third decoder based on instructions sent to a first decoder and the third decoder

Abstract

In a system large scale integrated circuit (LSI) according to one embodiment, management of the power supply, and the like, of a dedicated instruction processor can be carried out according to an instruction issued to a basic instruction processor at high speed. Further, the operational state of a dedicated instruction processor may be readily obtained by a basic instruction processor. In such a system LSI, a system controller () can include an instruction decoder () that decodes an instruction fetched by a basic instruction processor () and generates a decoder output. Such a decoder output can control a second power supply controlling unit (), a second clock signal generating unit (), a second program counter (), and a second conditional flag () for a dedicated instruction processor ().