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For the Inventor, By the Inventor

Nara, Japan

Hiroshi Matsubara

This inventor holds 5 USPTO granted patents. Top assignee: Sharp Kabushiki Kaisha Corporation. Active years: 1990-1999.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hiroshi Matsubara. Retrieved from https://idiyas.com/inventor/hiroshi-matsubara-o2l1lx80

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 5

% Patents Active = 100.0

Average Co-Inventor Count = 1.5

ph-index = 5

Forward Citations = 142(Granted Patents)


Location History:

  • Tenri, JP (1990 - 1991)
  • Nara, JP (1991 - 1999)

Company Filing History:

goldMedal5 out of 25,974 
 
Sharp Kabushiki Kaisha Corporation
 patents

Years Active: 1990-1999

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5 patents (USPTO):Explore Patents
1. 5877543 - Device assembly structure with reinforced outer leads (1999-03-02),
2. 5726501 - Semiconductor device having a solder drawing layer (1998-03-10),
3. 5065505 - Method for connecting circuit boards (1991-11-19),
4. 5034245 - Method of producing connection electrodes (1991-07-23),
5. 4963002 - Connection construction and method of manufacturing the same (1990-10-16),

Title: Innovations by Hiroshi Matsubara

Introduction

Hiroshi Matsubara is a notable inventor based in Nara, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of five patents. His work focuses on enhancing the reliability and efficiency of semiconductor devices.

Latest Patents

Matsubara's latest patents include a "Device assembly structure with reinforced outer leads." This invention provides a highly reliable assembly structure by reducing stress on the leads of a TCP device. The design incorporates a support ring that reinforces the soldered portion of the outer leads, effectively dispersing stress and preventing metal fatigue. Another significant patent is for a "Semiconductor device having a solder drawing layer." This device features a connection electrode and a solder bump that connects to a substrate electrode. The solder drawing layer retracts melted solder onto its surface, enhancing the device's performance.

Career Highlights

Hiroshi Matsubara is currently employed at Sharp Kabushiki Kaisha Corporation, where he continues to innovate in semiconductor technology. His work has been instrumental in developing reliable and efficient semiconductor devices.

Collaborations

Matsubara collaborates with talented coworkers, including Takashi Nukii and Yasunobu Tagusa. Their combined expertise contributes to the advancement of technology at Sharp.

Conclusion

Hiroshi Matsubara's contributions to semiconductor technology through his innovative patents demonstrate his commitment to enhancing device reliability and performance. His work continues to impact the industry positively.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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