The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 10, 1998

Filed:

Jun. 05, 1995
Applicant:
Inventor:

Hiroshi Matsubara, Nara, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
257778 ; 257737 ; 257779 ; 257772 ;
Abstract

A semiconductor device according to the present invention to be mounted on a mounting substrate includes: a connection electrode formed on a surface of the semiconductor device; a solder bump formed on the connection electrode, the solder bump electrically and mechanically connecting the connection electrode with a substrate electrode formed on the mounting substrate; and a solder drawing layer provided on the surface of the semiconductor device in a periphery of the solder bump and having a surface portion composed of a solder-agreeable metal, the solder drawing layer retracting melted solder of the solder bump onto a surface of the solder drawing layer by contact with the melted solder.


Find Patent Forward Citations

Matsubara, Hiroshi. (1998). Semiconductor device having a solder drawing layer (U.S. Patent No. 5726501). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5726501

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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