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For the Inventor, By the Inventor

Itami, Japan

Hiromasa Nakagawa

This inventor holds 8 USPTO granted patents. Top assignee: Mitsubishi Denki Kabushiki Kaisha. Active years: 1989-1997.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Hiromasa Nakagawa. Retrieved from https://idiyas.com/inventor/hiromasa-nakagawa

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 8

% Patents Active = 100.0

Average Co-Inventor Count = 2.7

ph-index = 5

Forward Citations = 83(Granted Patents)


Company Filing History:

goldMedal8 out of 21,351 
 
Mitsubishi Denki Kabushiki Kaisha
 patents

Years Active: 1989-1997

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8 patents (USPTO):Explore Patents
1. 5638537 - Cache system with access mode determination for prioritizing accesses to (1997-06-10),
2. 5544341 - Data access apparatus for preventing further cache access in case of an (1996-08-06),
3. 5535359 - Computer system with cache memory having address mask register (1996-07-09),
4. 5459852 - Cache bypass system with simultaneous initial transfer of target data to (1995-10-17),
5. 5454088 - Microprogram control device for controlling data path section including (1995-09-26),
6. 4908690 - Semiconductor integrated circuit device with high reliability wiring (1990-03-13),
7. 4899066 - OR-type CMOS logic circuit with fast precharging (1990-02-06),
8. 4807176 - Manchester type carry propagation circuit (1989-02-21),

Title: The Innovative Mind of Hiromasa Nakagawa

Introduction

Hiromasa Nakagawa is an accomplished inventor based in Itami, Japan, with a remarkable portfolio of 8 patents. His work primarily focuses on advancements in cache memory systems and data processing methods, contributing significantly to the fields of computer architecture and data management.

Latest Patents

Among his latest patents, Nakagawa has developed a cache system with access mode determination for prioritizing accesses. This system allows a cache memory to operate in different modes—one for cache hits and another for cache misses. The innovation features a condition setting circuit that differentiates between instruction and data caching, thereby optimizing performance based on the type of access. Another notable invention is a data access apparatus aimed at preventing further cache access during abnormal conditions, such as parity errors. This invention enhances the reliability of data transfer by halting the access process when an anomaly is detected, enabling immediate corrective actions by the central processing unit (CPU).

Career Highlights

Hiromasa Nakagawa currently works for Mitsubishi Electric Corporation, a leader in technology and innovation. Over the years, he has established himself as a prominent figure in the field, exemplifying creativity and engineering prowess through his patents and contributions to research and development.

Collaborations

Throughout his career, Nakagawa has collaborated with talented individuals such as Masayuki Hata and Akira Yamada. These partnerships have allowed for an exchange of ideas and expertise, bolstering innovation within their projects and enhancing the overall capabilities of their inventions.

Conclusion

Hiromasa Nakagawa's contributions to cache memory systems and data processing have had a profound impact on the technology industry. His patents reflect a deep understanding of the challenges faced in data management and represent a commitment to advancing technological solutions. As he continues to innovate, Nakagawa remains a vital figure in shaping the future of computer architecture.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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